Bu ered Steiner Tree Construction with Wire Sizing for Interconnect Layout Optimization

This paper presents an e cient algorithm for bu ered Steiner tree construction with wire sizing. Given a source and n sinks of a signal net, with given positions and a required arrival time associated with each sink, the algorithm nds a Steiner tree with bu er insertion and wire sizing so that the required arrival time (or timing slack) at the source is maximized. The unique contribution of our algorithm is that it performs Steiner tree construction, bu er insertion, and wire sizing simultaneously with consideration of both critical delay and total capacitance minimization by combining the performance-driven A-tree construction and dynamic programming based bu er insertion and wire sizing, while tree construction and the other delay minimization techniques were carried out independently in the past. Experimental results show the e ectiveness of our approach.